The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that is advantageous for element isolation.
Techniques for integrating a control circuit with a plurality of power transistors on the same semiconductor substrate have been developed for electronics devices such as portable devices and home appliances.
FIG. 1 is a schematic cross-sectional view of a vertical N-channel MOS (metal oxide semiconductor) transistor 300 described in Japanese Laid-Open Patent Publication No. 2003-303960. An epitaxial layer 33 is formed on a monocrystalline silicon substrate 32. Ion implantation and thermal diffusion are performed to form a diffusion buried layer 34 at the interface between the substrate 32 and the epitaxial layer 33. The epitaxial layer 33 includes a trench groove 39 extending in the depthwise direction of the epitaxial layer 33. A drain lead elect-rode 41 is formed in the trench groove 39 with an insulation film 38 arranged therebetween. The drain lead electrode 41 is electrically connected to the buried layer 34 and made of polycrystalline silicon. The epitaxial layer 33 further has a source region 45 and a channel region 44, which are formed through double diffusion. Gate electrodes 48 are formed to extend through the source region 45 and the channel region 44 with insulation films 47 arranged therebetween.
A plurality of semiconductor elements having the above-described structure are arranged on a semiconductor substrate. The semiconductor elements are electrically isolated from one another by a first isolation region 50 and a second isolation region 51. The first isolation region 50 is formed through ion implantation and thermal diffusion at the interface between the substrate 32 and the epitaxial layer 33. The second isolation region 51 is formed through ion implantation and thermal diffusion to extend from the surface of the epitaxial layer 33 to the first isolation region 50.
When voltage is applied to the gate electrodes 48, a conductive channel is formed in the channel region 44. Carriers of the MOS transistor 300 are electrons, which move from the source region 45, the channel region 44, the epitaxial layer 33, the buried layer 34, and to the drain lead electrode 41.
When current flows through the MOS transistor 300 shown in FIG. 1, leak current may leak into an adjacent element from a current flow path. This is referred to as a punch-through phenomenon. To improve the element breakdown voltage, that is, the insulation resistance required for element isolation, the isolation regions 50 and 51 must have a greater width in the lateral direction (the direction parallel to the surface of the semiconductor substrate). That is, the isolation regions 50 and 51 must have a greater diffusion width. For this reason, it is difficult to reduce the size of a semiconductor device.